1. Technical Field
The present disclosure relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
Electrostatic discharge (ESD) is a key factor affecting the reliability of integrated circuits. ESD is the rapid neutralization of electrical charges. The high electrostatic voltage in ESD can damage and cause failures in an integrated circuit. To protect the integrated circuit from damage due to ESD, an ESD protection circuit may be fabricated into the integrated circuit.
A gated diode has faster speeds, lower resistance, and higher fault current compared to a conventional STI (Shallow Trench Isolation) diode. Accordingly, the gated diode is increasingly being used in the ESD protection circuit.
FIG. 1 illustrates a gated diode of an ESD protection circuit in the prior art. Referring to FIG. 1, the gated diode is formed having a long striped pattern. The gated diode includes an active area comprising a P+ conductive region 1, a gate electrode 2, and an N+ conductive region 3. The length of the active area is given by W. The widths of the P+ conductive region 1, gate electrode 2, and N+ conductive region 3 are given by Lp, Lg, and Ln, respectively.
FIG. 2 is a cross-sectional view of the gated diode of FIG. 1. As shown in FIG. 2, conduction current in the gated diode flows from the P+ conductive region 1 to the N+ conductive region 3 (in the direction indicated by the arrows 4).
To obtain adequate ESD protection, the size of the gated diode needs to be increased. However, increasing the size of the gated diode may result in increased parasitic capacitance which could impact device performance. In particular, the performance degradation is more significant for high speed RF (Radio Frequency) integrated circuits.